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1. Commits on May 24, 2025

   • Merge pull request #1998 from mingtians/update-readme

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     aswaterman

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   • Update README with Zimop extension

     mingtians

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2. Commits on May 22, 2025

   • Merge pull request #1988 from binno/pr-aia

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3. Commits on May 21, 2025

   • Merge pull request #1997 from riscv-software-src/fix-1996

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   • Partially revert #1987 to fix regrssion in vsra.vi and vssra.vi

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     aswaterman

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   • Fix unused variable warnings

     aswaterman

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   • Merge pull request #1995 from arrv-sc/arrv-sc/fix-store-segfault

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4. Commits on May 20, 2025

   • fix: log store only if it actually happened

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     Alexander Romanov

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5. Commits on May 16, 2025

   • Merge pull request #1993 from arrv-sc/arrv-sc/init-blocksz

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     aswaterman

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   • Merge pull request #1990 from mslijepc/mslijepc_20250514_external-sim-ptr

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   • minor spacing fix

     mslijepc

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   • feat: move cache block size initialization to constructor

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     Alexander Romanov

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6. Commits on May 15, 2025

   • Merge pull request #1888 from tsewei-lin/vector-crypto-misaligned

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     aswaterman

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   • Merge pull request #1991 from arrv-sc/arrv-sc/const-get-isa

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   • Merge pull request #1992 from arrv-sc/arrv-sc/init-xlen

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   • Merge pull request #1989 from tianrui-wei/tianrui/decode_opcode

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   • vector: crypto: fix EMUL alignment check for .vs operations

     tsewei-lin

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   • vector: crypto: fix overlap check when EGW > VLEN

     tsewei-lin

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   • vector: crypto: fix constraint checks for vector-crypto instructions

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7. Commits on May 14, 2025

   • feat: initialize xlen in constructor

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     Alexander Romanov

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   • feat: mark processor_t getters as const

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     Alexander Romanov

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   • Merge branch 'riscv-software-src:master' into mslijepc_20250514_external-sim-ptr

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   • changing type of external_simulator member of external_sim_device_t

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   • Fix typo for implementation of AIA extension

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     binno

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   • Register hidelegh csr with aia_rv32_high_csr_t class

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     binno

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   • Modify non-standard interrupt start position

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     binno

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   • AIA: Raise virtual instruction exception on writing stimecmp (stimecmph) from VS-mode when hvictl.VTI=1

     

     YenHaoChen

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     binno

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   • AIA: Raise virtual instruction exception on acessing sie or sip (sieh or siph) from VS-mode when hvictl.VTI=1

     

     YenHaoChen

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     binno

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   • Smstateen: Implement *stateen0[59] controlling RV32-only CSRs (v)siph, (v)sieh, hidelegh, and hviph

     

     YenHaoChen

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     binno

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   • Smstateen: Implement *stateen0[59] controlling CSR stopi

     

     YenHaoChen

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     binno

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   • Smstateen: Implement *stateen0[59] controlling CSR vstopi

     

     YenHaoChen

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     binno

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   • Smstateen: Implement *stateen0[59] controlling CSRs hvien(h), hvictl, hviprio[12](h), and supervisor-level iprio array

     

     YenHaoChen

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     binno

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   • Smstateen: Implement *stateen0[60] controlling CSRs (v)siselect and (v)sireg

     

     YenHaoChen

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     binno

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   • AIA: Handle the interrupt of vstopi in VS-mode

     

     YenHaoChen

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     binno

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   • AIA: Allow interrupt of any IID from vstopi/hvictl

     

     YenHaoChen

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     binno

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