Lists (3)
Stars
AXI, AXI stream, Ethernet, and PCIe components in System Verilog
[BRH YT CHANNEL] This repo contains all the code and ressources you need for the Zynq tutorials, ready to copy and paste.
Learn how to build our own RV32I core, verify it and actually use it. From scratch & with more than 200 pages of detailed tutorial with schemes & explanation.
ChipWhisperer - the complete open-source toolchain for side-channel power analysis and glitching attacks
NCTU 2021 Spring Integrated Circuit Design Laboratory
This is my sandbox for experimenting with the features offered by the AMD (Xilinx) FreeRTOS port. The main platform used is the Digilent Zybo-z7-20. The implemented system is quite simple, comprisi…
Low-Precision YOLO on PYNQ with FINN
Extra tools to make life easier with bitbake
miscellaneous fpga experiments to support other projects
Proposed RISC-V Composable Custom Extensions Specification
SYCL for Vitis: Experimental fusion of triSYCL with Intel SYCL oneAPI DPC++ up-streaming effort into Clang/LLVM
blaze is a Rust library for ZK acceleration on Xilinx FPGAs.
Open-source RISC-V microcontroller for embedded and FPGA applications
The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configurations are capable of booting Linux.
Latest in the line of the E32 processors with better/generic cache placement
OpenSource GPU, in Verilog, loosely based on RISC-V ISA
Hardware implementation of the SHA256 algorithm using AXI bus interconnect on the Xilinx Artix 7 (Basys 3 development board).
The project description of this project was the major project in the Computer Architecture course. It's a RISC-V processor and tested on Nexys A7 kit.
An acceleration engine for proving SNARKS over the bn128 curve, targeted for AWS FPGAs
4 stage, in-order, secure RISC-V core based on the CV32E40P