Chisel: A Modern Hardware Design Language

Export Python description from the systemrdl-compiler register model

Build Customized FPGA Implementations for Vivado

SystemVerilog compiler and language services

Control and status register code generator toolchain

cocotb: Python-based chip (RTL) verification

SystemRDL 2.0 language compiler front-end

An abstraction library for interfacing EDA tools

FireSim: Fast and Effortless FPGA-accelerated Hardware Simulation with On-Prem and Cloud Flexibility

Berkeley's Spatial Array Generator

Verilog Ethernet components for FPGA implementation

A wiki plugin for Vim

Antmicro's fast, vendor-neutral DMA IP in Chisel

A Library of Chisel3 Tools for Digital Signal Processing

Package manager and build abstraction tool for FPGA/ASIC development

Sphinx domain to allow integration of Verilog / SystemVerilog documentation into Sphinx.

SkySafe Miscellaneous Reverse Engineering Blog

Dataset of Linus Torvalds' rants classified by negativity using sentiment analysis

A tiling window manager based on binary space partitioning

This repository provides state of the art (SoTA) results for all machine learning problems. We do our best to keep this repository up to date. If you do find a problem's SoTA result is out of date …