opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

HDL libraries and projects

The Ultra-Low Power RISC-V Core

Verilog library for ASIC and FPGA designers

Repository for basic (and not so basic) Verilog blocks with high re-use potential

The USRP™ Hardware Driver FPGA Repository

5-stage pipelined 32-bit MIPS microprocessor in Verilog

我的数字IC厂库：Verilog HDL; System Vreilog; UVM; ModelSim; Quartus II;

DDR2 memory controller written in Verilog

北京工商大学 人工智能学院 数字系统与逻辑设计 (2022-2023-1 | 孙梅) 及 FPGA 技术及应用 (2022-2023-2 | 孙梅) 课程作业

Some basic hardware and logic designs and their respective testbenches written in Verilog HDL