Converter Design for Electrolytic capacitor-less Two Stage PV System - Undergraduate Research Project @ VLPERI, IIT(BHU)

Coding challenge for LFX Mentorship Fall-2022.

Essentials of Data Structures and Algorithms

Trying out cocotb - Tuts and Example

A simple implementation of a RISC-V core (RV32I) written in TL Verilog.

A RISC-V Mixed Signal System-on-Chip(SoC) produced by integrating RVMyth RISC-V Core with Phase Locked Loop(PLL) as a clock multiplier

My learning progress, visualised with projects I've made while learning

Morse Code Decoder using Digital Logic

Instance Segmentation using Mask RCNN(with pretrained weights of COCO dataset)