Neurônio Perceptron feito em Javascript (vanilla)

Implementação de um Perceptron em R e em Javascript, o funcionamento pode ser visto no site abaixo

The T80 (VHDL) synthesizable soft core of Zilog Z80 (forked from http://opencores.org/project,t80)

Disassembly of Sonic 1 ("Sonic the Hedgehog", 8-bit) for the SEGA Master System in OZ80 ('OZ80MANDIAS') format

Master System Sonic 1 Disassembly

Learn how to design digital systems and synthesize them into an FPGA using only opensource tools

Z80 CPU for OpenFPGAs, with Icestudio

An Operating System for Z80 computers, written in assembly

Sinclair ZX Spectrum 48k and 128k on an Altera DE1 FPGA board

Visual Zilog Z80 netlist-level simulator

An implementation of the Z80 CPU for Altera, Xilinx and Lattice FPGAs

A csharp emulator for the Zilog Z80 CPU

Highly portable Zilog Z80 CPU emulator written in ANSI C

nes emulator based on VHDL

How to generate NTSC compliant(?) composite color video with an FPGA

VHDL implementation of an Atari 2600

https://stirring-kataifi-5a7982.netlify.app/

Descrição em VHDL de um processador baseado no Mips

Instrumented MIPS kernel

5-stage pipelined 32-bit MIPS microprocessor in Verilog

A MIPS32 CPU implemented by VHDL

It is a program to simulate the behavior of MIPS machine written in C. It can run most of the instructions in the MIPS instruction set

A Simulative MIPS CPU running on Logisim.

A classic 5-stage pipeline MIPS 32-bit processor, including a 2-bit branch predictor, a branch prediction buffer and a direct-mapped cache.

MIPS CPU implemented in Verilog

It is a Mips 32 bits Multicicle project. It was developed for Computer Organization class at UERGS (Rio Grande do Sul State University). It has a memory with 512 cells of 8 bits each one. This proj…

This code illustrate a way to convert an integer number of 32 bits in a float number of 32 bits. This float number is on IEEE 745 pattern for a word of 32 bits.

I'm postgraduate in IT Governance, graduate in Computer Sciences at Estácio University, in HR at Leonardo Da Vinci University and studying bachelor in Computer Engineering at UERGS.

Mips compiler developed for Computer Organization class at UERGS (Rio Grande do Sul State University). It returns a memory code to cut and paste on the VHDL memory file. Simply and easy. Built usin…

It is a Mips 32bits Multicicle. It was developed for Computer Organization class at UERGS (Rio Grande do Sul State University). It has a memory with 512 cells of 8bits each one. This project was wr…