Skip to content
View jaycien's full-sized avatar
4 followers · 97 following

Block or report jaycien

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Maximum 250 characters. Please don't include any personal information such as legal names or email addresses. Markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse
@vortexgpgpu
Vortex OpenGPU vortexgpgpu
@LiAutoAD
LiAutoAD
@google-coral
google-coral google-coral
Open source projects for coral.ai

San Francisco, CA

@preservim
PreserVIM preservim
We don't let bit rot creep into great vim plugins, we preserve 'em!
@Infineon
Infineon Infineon

Neubiberg, Germany

@IPRC-DIP
IPRC-DIP
@olofk
Olof Kindgren olofk
@Xilinx
Xilinx Xilinx
GitHub.Com/Xilinx/

San Jose, CA

@scarv
SCARV scarv
a side-channel hardened RISC-V platform
@Wren6991
Luke Wren Wren6991
Interests: C, Verilog, Python Dislikes: C, Verilog, Python

Cambridge, UK

@fusesoc
fusesoc
@open-design
open-design
@lgeek
Cosmin Gorgovan lgeek

Manchester, UK

@habibagamal
Habiba Bassem habibagamal
Software engineer at Microsoft.

Cairo, Egypt

@regymm
regymm regymm
Post-undergrad amateur programmer

Univ. of Sci. & Tech. of China Forever

@gzzyyxh
Xiuhua Yang gzzyyxh
BS, Electronic Engineering

Fudan University Shanghai, China

@XUANTIE-RV
达摩院玄铁 XUANTIE-RV
@StanfordAHA
Stanford AHA! Agile Hardware Center StanfordAHA
Making hardware fun again

Stanford University

@edabk-hust
EDABK edabk-hust
Nhóm nghiên cứu EDABK, Đại học Bách Khoa Hà Nội

P611 Thư viện Tạ Quang Bửu, ĐH Bách Khoa HN, 1 Đại Cồ Việt, Hà Nội, Việt Nam

@erwanregy
Erwan Hanis Régy erwanregy

@arm United Kingdom

@black-parrot
Black Parrot black-parrot
The Black Parrot RISC-V Linux-Capable Multicore
@IHP-GmbH
IHP - Leibniz-Institut für innovative Mikroelektronik IHP-GmbH

Germany

@YosysHQ
Yosys Headquarters YosysHQ
Yosys Open SYnthesis Suite
@NYU-Processor-Design
NYU Processor Design NYU-Processor-Design
NYU Processor Design VIP team

United States of America

@The-OpenROAD-Project
The OpenROAD Project The-OpenROAD-Project
OpenROAD seeks to develop and foster an autonomous, 24-hour, open-source layout generation flow (RTL-to-GDS).

United States of America

@mballance
Matthew Ballance mballance

AMD Portland, Oregon

@veryl-lang
veryl-lang
@tom-urkin
Tom Urkin tom-urkin
PhD student at Ben Gurion University, Israel. I'm occasionally uploading spare time projects to this github page - feel free to use the source codes :)
@stnolting
stnolting
Roads? Where we're going we don't need roads. - "Doc" Emmett L. Brown
@ucb-bar
UC Berkeley Architecture Research ucb-bar

Berkeley, CA

@efabless
Efabless efabless

Anywhere

@adki
Ando Ki adki
Working for KAIST as an adjunct professor since May 2020. Working for Future Design Systems as the CEO and President since May 2017.

Future Design Systems Daejeon, Korea

@openhwgroup
OpenHW Group openhwgroup

Ottawa, Ontario, Canada

@chili-chips-ba
Chili.CHIPS chili-chips-ba
Making math audible, visible, tangible in a number of big.LITTLE ways, we're engineers, entrepreneurs, creatives who love 2 think up & fire up FPGA, CPU, NPU...

Chili.CHIPS*ba Bosnia-Herzegovina

@VLSIDA
VLSI Design & Automation Group VLSIDA
UC Santa Cruz VLSI Design and Automation research lab

Santa Cruz, CA

@4DV4NC3M3N7
Hans_Pham 4DV4NC3M3N7
love tech and futurism currently interested in RISC-V.

HCM University of Technology Ho Chi Minh city, Viet Nam

@IC-Design-Lab
OpenIC IC-Design-Lab
ICS (Integrated Circuit and System) is a research team with expertise in ASIC/FPGA/SoC Design and Hardware Acceleration on HPC.

LBL-UHCL-ICS Houston, TX

@zhajio1988
Jude Zhang zhajio1988
A digital verification engineer.

Freestyle

@bytedance
Bytedance Inc. bytedance

Singapore

@rggen
RgGen rggen
Code generation tool for control and status registers
@PacoReinaCampo
Francisco Javier Reina Campo PacoReinaCampo
I am an Electronic Engineer specialized in digital design and verification, with emphasis on Hardware Description Languages ((System)Verilog, VHDL).

QueenField Abu Dhabi

@opensocdebug
Open SoC Debug opensocdebug
Open SoC Debug provides building blocks for SoC debug systems

Your SoC!

@merledu
Micro Electronics Research Laboratory merledu
A non-profit organization fostering research on IoT, AI, and ML-based architectures leveraging the open-source RISC-V ISA.

Pakistan

@OSCPU
Open Source Chip Project by University (OSCPU) OSCPU
Let students design their own chips!
@hizbi-github
Hizbullah Khan hizbi-github
VoIP/DevOps. Projects include automation software, web scrapers, and some micro-controllers/FPGA development.
@Purdue-SoCET
Purdue System on Chip Extension Technologies Purdue-SoCET
A student team working on designing and testing an SoC at Purdue University

West Lafayette, Indiana

@PXVI
k-sva PXVI
@RoaLogic
Roa Logic BV RoaLogic
@taichi-ishitani
Taichi Ishitani taichi-ishitani

@pezy-computing Kanagawa, Japan

@WilsonChen003
Wilson Chen WilsonChen003
an IC engineer with 22+ years on GPU & SOC. Interested on IP/ASIC/SOC arch & design & verification & flow

Shanghai