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1. GN-hdl_axi4l_test GN-hdl_axi4l_test Public

   AXI4-Lite register module and assertion-based verification environment.

   SystemVerilog 1

2. GN-mdl_clock GN-mdl_clock Public

   Parameterized clock generator model for RTL simulation.

   SystemVerilog

3. GN-mdl_reset GN-mdl_reset Public

   Reset generator model for RTL simulation environments.

   SystemVerilog

4. GN-mdl_axi4_stream GN-mdl_axi4_stream Public

   AXI4-Stream master/slave verification models with task-based transaction control.

   SystemVerilog

5. GN-hdl_common_test GN-hdl_common_test Public

   SystemVerilog-based common testbench and assertion framework for RTL verification.

   SystemVerilog

6. GN-sim_questa_env GN-sim_questa_env Public

   PowerShell-based simulation environment for Questa Prime Lite.

   Python