This repository contains the source code for an LC2K CPU implemented in Verilog.
LC2K design is from EECS 370 Course @ University of Michigan - Ann Arbor.
LC2K ISA supports 32-bit address, 8 registors, and 8 opcodes.
The LC2K assembly language program can be run using iverilog vvp command.
iverilog -o dsn ALU_ValB_Mux.v ALU.v Clock.V Control_ROM.v CPU.v Data_Memory.v Instr_Memory.v Program_Counter.v Program_Mux.v Reg_Memory.v Sign_Extend.v Write_Data_Mux.v Write_Reg_Mux.v
vvp dsn
With $monitor display, I was able to produce the log of value changes in register 1. In the following program, REG1 begins with loading the value of 5 [PC=0], and inside the loop, it decreases by 1 until the value equals 2 [PC=3-5]. Then, the program performs load and store actions where the value of REG1 becomes 7 [PC=7-9]. Finally, REG1 loads the changed value from memory and gets the value 2 [PC=10].
A VCD file was also generated to check the working functionality of all individual modules.
I have used Tang Nano 20k FPGA to run my CPU and a demo program. Tang Nano 20k is a Gowin FPGA based board, so I used Gowin EDA to synthesize the code and hooked up some LEDs to check it working. https://youtu.be/ApysinIOpjY
- Run it on FPGA
- Multicycle Implementation
- Pipeline Implementation