HardPy is a python library for creating a test bench for devices.

🚜 Collect of CAN IDs and its payloads for various car brands/models in one place. Might be useful for Cyber Security Researchers, Reverse Engineers, and Automotive Electronics Enthusiasts.

📦 Tool to enable package managing for HDL VIP or IP cores (Verilog, SystemVerilog, VHDL) using Python pip

Ирина - русский голосовой ассистент для работы оффлайн. Поддерживает скиллы через плагины.

Плагины для голосового помощника Ирина

Compact and Minimal LaTeX Resume Template

Verilog Ethernet components for FPGA implementation

All code found on nandland is here. underconstruction.gif

🔴 SystemVerilog FPGA cores to communicate with FTDI Synchronous/Asynchronous FIFOs (FT245 protocol)

Verilog implementation of RISC-V: RV32IAC plus much of B. 32-bit or 16-bit bus.

LiteX boards files

Программа для создания карты для сборки картинки из лего-деталек

100kHz to 6GHz 2 port USB based VNA

Buildroot config for EBAZ4205

EBAZ4205 is Xilinx Zynq based mining board used in Ebang Ebit E9+ bitcoin miner machine.

Open source machine learning accelerators

Распакованный код репозитория с кодом ДЭГ 2021

Control and Status Register map generator for HDL projects

Theory of digital signal processing (DSP): signals, filtration (IIR, FIR, CIC, MAF), transforms (FFT, DFT, Hilbert, Z-transform) etc.

Universal utility for programming FPGA

Hardware design files for Betrusted

VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!

Interactive HTML BOM generation plugin for KiCad, EasyEDA, Eagle, Fusion360 and Allegro PCB designer

A git-friendly Vivado wrapper

open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software

This is a guide for bringing up custom ZYNQ boards. It covers test sequence, test method, common error situations and code and project that can help to investigate a bring-up problem.