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2 stars written in VHDL
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rhexsel / cmips

All things related to cMIPS, a synthesizable VHDL model for the 5-stage pipeline, MIPS32r2 core.

VHDL 13 5 Updated Jun 8, 2019

OpenMixerProject / AES50

Forked from YetAnotherElectronicsChannel/AES50

An IP-Core for AES50 protocol

VHDL 6 1 Updated Mar 28, 2026