Skip to content
View kabylkas's full-sized avatar

Organizations

@masc-ucsc

Block or report kabylkas

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Maximum 250 characters. Please don’t include any personal information such as legal names or email addresses. Markdown is supported. This note will only be visible to you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse
Showing results

Memory Marionette Model

C++ 8 Updated Oct 17, 2025

A free audio dataset of spoken digits. An audio version of MNIST.

Python 677 249 Updated May 2, 2024

AI assisted tool to randomize states of the hardware while executing tests

Filebench WML 7 Updated Apr 7, 2025

Utilities for accessing AMD's Machine-Readable GPU ISA Specifications.

C++ 53 4 Updated Apr 9, 2026

Simple risc-v emulator, able to run linux, written in C.

C 150 23 Updated Apr 11, 2024

The fastest Trust Layer for AI Agents

Python 153 20 Updated Feb 3, 2026

FPGA exercise for beginners

Verilog 174 125 Updated Jun 12, 2026

Memory Marionette Model

C++ 4 1 Updated Aug 27, 2023

Instruction Set Generator initially contributed by Futurewei

C++ 308 77 Updated Oct 17, 2023

The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configurations are capable of booting Linux.

Assembly 2,970 961 Updated Jun 15, 2026

RISC-V RV64GC emulator designed for RTL co-simulation

C++ 242 67 Updated Nov 20, 2024

Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation

C++ 238 58 Updated Jun 15, 2026