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1. Qu Qu Public

   The Qu Processor: Superscalar, out-of-order, speculative, 32 bit, RISC-V. Aims to be based on M1 Firestorm. Still wildly incomplete.

   SystemVerilog 5 1

2. TPU.sv TPU.sv Public

   Anatomy of a powerhouse: SystemVerilog TPU based on Google TPU v1

   SystemVerilog 22 1

3. v60 v60 Public

   Macro placement for the GPU era: v60 is a multi-stage, analytical, GPU-accelerated macro placement algorithm.

   Python

4. V-FRONT V-FRONT Public

   Five-stage 32-bit RISC-V CPU in Verilog (Educational, RV32I 2.1 compliant, Zicsr, Zifencei)

   C 3 1

5. clairvoyant clairvoyant Public

   Image super-resolution carved into silicon (FPGA Ignite 2024)

   VHDL 1

6. advent-of-fpga-2025 advent-of-fpga-2025 Public

   Decorating the North Pole in Hardcaml: My submission for the Advent of FPGA 2025 challenge from Jane Street

   OCaml