From FPGA Gates to Scientific Calculator

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You can run it on pynq z1. The repository contains the relevant Verilog code, Vivado configuration and C code for sdk testing. The size of the systolic array can be changed, now it is 16X16.

A group project for the Advanced AI module in Trinity College Dublin. A pong agent is trained through the Q-learning algorithm with a Swin transformer backbone and compared against a CNN model from…

A complete computer science study plan to become a software engineer.

Implement a ChatGPT-like LLM in PyTorch from scratch, step by step

[HPCA 2023] ViTCoD: Vision Transformer Acceleration via Dedicated Algorithm and Accelerator Co-Design

FPGA based Vision Transformer accelerator (Harvard CS205)

Pytorch reimplementation of the Vision Transformer (An Image is Worth 16x16 Words: Transformers for Image Recognition at Scale)

The largest collection of PyTorch image encoders / backbones. Including train, eval, inference, export scripts, and pretrained weights -- ResNet, ResNeXT, EfficientNet, NFNet, Vision Transformer (V…

This project implements a hardware-accelerated matrix multiplication using High-Level Synthesis (HLS). The design is optimized for FPGA implementation and utilizes on-chip BRAM for efficient data s…

Interactive deep learning book with multi-framework code, math, and discussions. Adopted at 500 universities from 70 countries including Stanford, MIT, Harvard, and Cambridge.

Reinforcement Learning Tutorial with Demo: DP (Policy and Value Iteration), Monte Carlo, TD Learning (SARSA, QLearning), Function Approximation, Policy Gradient, DQN, Imitation, Meta Learning, Pape…

Team for Advanced AI module.

[ASAP 2020; FPGA 2020] Hardware architecture to accelerate GNNs (common IP modules for minibatch training and full batch inference)

This is a verilog implementation of 4x4 systolic array multiplier

Final Project for Digital Systems Design Course, Fall 2020