SERV - The SErial RISC-V CPU

A small, light weight, RISC CPU soft core

RISC-V XV6/Linux SoC, marchID: 0x2b

3-stage RV32IMACZb* processor with debug

Various HDL (Verilog) IP Cores

RISC-V Formal Verification Framework

A Verilog HDL model of the MOS 6502 CPU

All code found on nandland is here. underconstruction.gif

Examples for iCE40 UltraPlus FPGA: BRAM, SPRAM, SPI, flash, DSP and a working RISC-V implementation

Various iCE40 cores / projects to play around with (mostly targeted at the icebreaker)

Single/Multi-channel Full Speed USB interface for FPGA and ASIC designs

Support files for participating in a Fomu workshop

Revengineered ancient PDP-11 CPUs, originals and clones

i8080 precise replica in Verilog, based on reverse engineering of real die

This repository contains small example designs that can be used with the open source icestorm flow.

A compact USB HID host FPGA core supporting keyboards, mice and gamepads.

Gateware / Firmware / BuildRoot to run linux on iCE40 / iCEBreaker

USB DFU bootloader gateware / firmware for FPGAs

Dual-issue RV64IM processor for fun & learning

ice40 USB Analyzer

An automatic clock gating utility

1801 series ULA reverse engineering

"Designing Video Game Hardware in Verilog" in iCE40HX8K Breakout Board.

It is a fpga implementation of an i2c master, framebuffer for sdd1306 display

Test projects for the OrangeCrab ECP5 FPGA board

The set of cleaned-up examples based on 2017 trainings in Kiev, Novosibirsk, Tomsk, Novosibirsk and Astana