a super regular RISC that encodes constants in immediate blocks.

Figure 1 - instruction (pc-relative) and constant (ib-relative) streams

glyph is a proposed computer architecture that emphasizes simplicity, efficiency, and flexibility. unlike typical processors, it separates instructions from constants, which can make programs smaller and faster to execute. it uses a compact, regular instruction format and a small 'predicate' register for control flow. the design carefully considers how a processor reads, interprets, and executes instructions.

this list outlines architectural highlights of the glyph architecture:

• simplified decode - instruction decode is dramatically simpler than CISC architectures.
• constant blocks - increase fetch bandwidth and speed up dynamic linking.
• true carry - simplifies big integer carry-add arithmetic used for cryptography.
• divide-by-zero branch - eliminates conditional branch instructions before divisions.
• simplified vector SIMD - 64-bit instruction packets support AVX10-like vector SIMD.
• arithmetic vector swizzle - speeds up subgroup shuffle operations for vector arithmetic.
• capabilities and domains - provide context switching and page-table color permissions.
• privilege level free - uses capabilities and domains to abstract privilege levels.
• page table colors - for zoned physical memory and address translation permissions.
• message-signaled interrupts - support globally-scoped inter-domain message interrupts.
• multicast network-on-chip - enables synchronized messaging for thread groups.
• deadline timer interrupts - uses the processor time stamp counter for deadline timers.
• muliple page sizes - supports 4KiB, 16KiB, and 64KiB page sizes to ease emulation.
• software-defined MMU - accelerated address translation for foreign page-table formats.
• address-space prefixes - enable support for OpenCL high-speed local memory.
• virtual machine definition - EFI, ACPI, device-tree, and VirtIO device support.
• comprehensible specification - semantic normalization with ARPA naming conventions.

glyph is a super-regular RISC architecture that encodes constants in a secondary constant stream accessed via an immediate base (ib) register that points to immediate blocks containing constants. the (ib) register can branch like the program counter (pc), and call instructions set (pc, ib) simultaneously for procedure calls.

glyph uses relative addresses in its link register, allowing branch instructions to pack (pc, ib) displacements for compatibility with a single link register. this is achieved by packing two 32-bit relative (pc, ib) displacements into an i32x2 vector. a 128-bit version of the instruction set relaxes this relative address requirement.

glyph immediate blocks can be chained using relative displacements and switched via the constant branch instruction. unlike typical RISC architectures, immediate blocks containing constants allow relocations to be word-sized, following C-style packing and alignment rules.

this list outlines differentiating features of the glyph architecture:

• variable length instruction format supporting 16, 32, and 64-bit instructions.
• 16-bit compressed instruction packets that can access 8 registers.
• 1-bit predicate for compare, branch, divide-by-zero, and add or subtract with carry.
• (pc,ib) is a program counter and immediate base register address vector.
• link register contains a packed relative (pc,ib) address vector to function entry.
• ibj (immediate-block-jump) adds a relative address to the immediate base register.
• mov (move-word) uses a displacement to access an immediate block constant.
• jal (jump-and-link) links address and adds immediate block constants to (pc,ib).
• jtl (jump-to-link) subtracts link vector and adds immediate block constants to (pc,ib).
• pin (pack-indirect) packs two absolute addresses as relative address vector from (pc,ib).

compiled versions of the architecture specification are available from the following URLs:

• current: glyph.pdf
• latest: glyph-20260610.pdf

this list outlines instructions, opcodes, and descriptions used in the 16-bit compressed instruction packet:

glyph uses a super regular RISC encoding designed for vectorized decoders. the variable length instruction encoding supports 16-bit, 32-bit, 64-bit, and 128-bit instruction packets. each 16-bit packet has 2-bits for size. in contrast, RISC-V currently has a variable size field which requires up to 7-bits for 64-bit instruction packets. glyph size decoding logic is simpler and easily supports 16-wide decoders (256-bits) with 8x32-bit instructions. for this reason, glyph does not support 48-bit instructions.

Figure 2 - one, two, and three operand 16-bit instruction formats

Figure 3 - one, two, and three operand 32-bit instruction formats

Figure 4 - one, two, and three operand 64-bit instruction formats

this repository contains three implementations of the super regular RISC architecture. there is a simple interpreter written in C, another one written in Go, and a reference interpreter written in Python.

the simple interpreter in C can be built using CMake. presently the implementation is constrained to inline functions in one header.

cmake -B build -G Ninja -DCMAKE_BUILD_TYPE=RelWithDebInfo
cmake --build build

the simple interpreter in C, the Go interpreter and the reference interpreter in Python all support the 16-bit compressed opcodes and can be launched using the test script which runs all three then diffs the output of the tests to perform differential testing between them.

python3 scripts/test.py

this Python script allows one to explore the combinatorial decode window for various widths using 16-bit alignment for instructions. the following invocation prints the decode offsets for a 4-wide 64-bit decoder.

./scripts/combo.py --print-decode -w 4

Figure 5 - screenshot showing partial output from combos.py