Standalone IP with ARM-AMBA/AXI capable device. Enables sending and receiving data via SpaceWire protocol. Tested on Xilinx FPGA (ZYNQ).

Python SpaceWire Library

C library for serializing and deserializing SpaceWire RMAP commands and replies

SpaceWire Light

Open-source C++ library for the SpaceWire and RMAP protocols

IP Core Library - Published and maintained by the Open Source VHDL Group

Common SystemVerilog components

We write your reusable computer vision tools. 💜

AXI, AXI stream, Ethernet, and PCIe components in System Verilog

Instructions for enabling USB (ethernet) gadget mode on RPi 4 and RPi Zero 2W.

Open-source high-performance RISC-V processor

bladeRF-wiphy is an open-source IEEE 802.11 compatible software defined radio VHDL modem

Open Logic FPGA Standard Library

Collection of all FPGA related PSI libraries in the correct folder strucutre. Each library is included as submodule.

A huge VHDL library for FPGA and digital ASIC development

A collection of reusable, high-quality, peer-reviewed VHDL building blocks.

Verilog AXI stream components for FPGA implementation

Verilog Content Addressable Memory Module

Xilinx Embedded Software (embeddedsw) Development

HDL and C source for WAVE Zynq Ultrascale+ SoC

Open source Altium Database Library with over 200,000 high quality components and full 3d models.

Python-based Hardware Design Processing Toolkit for Verilog HDL

The UVM written in Python

Official OpenOCD Read-Only Mirror (no pull requests)

Code generation tool for control and status registers

Build your hardware, easily!

RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT

A FPGA friendly 32 bit RISC-V CPU implementation

Fully Open Source FASOC generators built on top of open-source EDA tools