A collection of VHDL designs examples for digital circuits

• 📖 About
• 🙏 Acknowledgements
• 🧩 Designs
• 📦 Structure
• 🔧 Tools
• ✈️ Usage
  • 🚀 Simulate
  • 🧪 Check & Analyze
• 📚 Resources
• ✔️ To-do
• 📜 License

This repository contains a collection of VHDL circuit examples for digital design course.

These designs are reusable and suitable for a variety of computing and electronics projects, and they were build during my computer science and electronics classes as part of my engineering degree.

Some designs might have multiple architecture implementations to show design options and variations. Basic test bench examples are also given for some circuits.

• My school's professors, for introducing me to this "language" and the lessons that came with it.
• VHDL Digital Design - Took inspiration for the Makefile and some VHDL designs. I've stumbled upon this repo while re-structuring mine and looking for already existing ones.

• Directories

  • .vscode - Project specific VSCode settings (formatting and extensions)
  • rtl - VHDL designs and circuits (.vhd)
  • tb - VHDL test bench files
  • doc - Documentation (on its way, but not yet ...)

• Files

  • flake.nix - Environment configuration (based on dev-templates)
  • .envrc - Used by direnv to load Flakes
  • flake.lock - Used by Flakes to version packages
  • Makefile - Used to automate checks and analyses

• VSCodium - Code editor
• GHDL - VHDL 2008/93/87 simulator
• VUnit - Testing framework for VHDL
• NVC - VHDL compiler & simulator
• GTKWave - Waveform viewer

1. All the files under rtl/ and tb/ can be imported in your synthesis tool (e.g Quartus or Vivado).
2. Optionally, you can use GHDL, which is a cross-platform open-source simulator for VHDL language, to simulate the circuits.
3. Install GHDL and GTKWave and add them to your PATH
4. Simulated results can be viewed using GTKWave which is an open source waveform viewer.

Run make simulate ARCHNAME=tbname to run the given testbench and display waveform using GTKWave where tbname is any of the testbench names inside the tb directory.

$ make simulate ARCHNAME=tb_counter
>>> cleaning design...
>>> done...
>>> analyzing designs...
>>> simulating design: tb/tb_counter.vhd
tb/tb_counter.vhd:43:9:@510ns:(assertion note): completed
>>> showing waveform for: tb/tb_counter.vhd

GTKWave Analyzer v3.3.94 (w)1999-2018 BSI
...

100us stop time is given for simulation by default. Optional STOPTIME= argument can be passed to Makefile to change this value.

make simulate ARCHNAME=tb_counter STOPTIME=1ms

Run make on the root folder to check syntax and analyze all designs :

$ make
>>> check syntax on all designs...
>>> analyzing designs...
>>> completed...

• My college classes
• This old repo I've stumbled upon while searching for other similar repos
• This excellent blog post and how to set up a VHDL environment

• Implement test benches for all designs

This project is licensed under the MIT License - see the LICENSE file for details.