VHDL 2008/93/87 simulator

Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

Bitburner Game

Nim for GDExtension — a pure library and CLI tool.

An ecosystem of tools for Godot Engine and Valve's Steam. For Linux, Mac, and Windows.

Nim bindings for Godot Engine

Rust support for a CPU I made

Load or create saves for the game Turing Complete

CFD database for Formula Student is here.

Primary Git Repository for the Zephyr Project. Zephyr is a new generation, scalable, optimized, secure RTOS for multiple hardware architectures.

conv_visualizer

The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configurations are capable of booting Linux.

Ariane is a 6-stage RISC-V CPU

Ariane is a 6-stage RISC-V CPU capable of booting Linux

Curated list of project-based tutorials

A 16-bit RISC CPU inspired by MIPS. I designed this to learn more about computer architecture/organization.

Example code for HTML, CSS, and Javascript for Web Developers Coursera Course

LLM inference in C/C++

修論・博論のTeXのスタイル これをforkして書き始めると良い

Rewrite of ModMyFactory, the Factorio mod manager

This project aims to enhance the working environment on Windows

Ranking Google Scholar search results based on the number of citations

SERV - The SErial RISC-V CPU

A very simple and easy to understand RISC-V core.

Accompanying live info and links for VLSI Design Systems and Redwood EDA "Microprocessor for You in Thirty Hours" Workshop