A scalable 256/1024-RISC-V-core system with low-latency access into shared L1 memory.

Macro Placement - benchmarks, evaluators, and reproducible results from leading methods in open source

A better build tool for Java, Scala and Kotlin: Simpler than Maven, easier than Gradle, with 3-7x faster dev workflows than other JVM build tools

Chisel: A Modern Hardware Design Language

SystemVerilog to Verilog conversion

ISPD26 Contest: Post-Placement Buffering and Sizing

SonicBOOM: The Berkeley Out-of-Order Machine

Open-source high-performance RISC-V processor

RTL, Cmodel, and testbench for NVDLA

The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configurations are capable of booting Linux.

A Linux-capable RISC-V multicore for and by the world

A FPGA friendly 32 bit RISC-V CPU implementation

A collection of tests and benchmarks for the Arc simulation backend of CIRCT

Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

SystemVerilog compiler and language services

The next generation of OpenLane, rewritten from scratch with a modular architecture

OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

This GitHub repo is for the OpenROAD and CircuitOps Tutorial at ASP-DAC 2024

CircuitNet: An Open-Source Dataset for Machine Learning Applications in Electronic Design Automation (EDA)

OpenABC-D is a large-scale labeled dataset generated by synthesizing open source hardware IPs. This dataset can be used for various graph level prediction problems in chip design.

An Open-Source Analytical Placer for Large Scale Heterogeneous FPGAs using Deep-Learning Toolkit

Deep learning toolkit-enabled VLSI placement

Modular hardware build system

Circuit IR Compilers and Tools

Rocket Chip Generator

tcad extension for dac22 netlist contrastive learning

机器学习、深度学习的学习路径及知识总结

reference block design for the ASAP7nm library in Cadence Innovus