Emily 💞
emilycodestar
I commit on the first date. 🚩 My code is cleaner than your browser history. Check my repos if you think you can handle a merge conflict with me. 💅🐍
Conor
Conchobhar42
Electronic Eng.-Worked Video/Comm R&D PCB Design & Testing new ASIC. In2 MixedSig/DSP/SDR/Audio Hard/Soft(C,HDL) Newb->Python, Swift, Metal, JUCE, FPGA, GPU, ML
Cambridge, Ontario Canada
Ammar Saleem
ammarsaleem22
Hardware Design Engineer I Amaranth HDL l Verilog l Python l FPGAs l RISC-V
Micro Electronic Research Lab Pakistan
Yan
TheFanatr
I have a very good description you can find here: https://goo.gl/sTBRL6 . It pretty much sums everything up.
\Device\HardDisk1
Owen Lamont
owenlamont
I'm a software engineer with interests in data visualisation, machine learning, computer graphics, Python, and Rust
OptiGrid Perth, Australia
Jevin Sweval
jevinskie
Senior Security Researcher, compilers/optimizations/[de]obfuscation, SCA, program analysis, NFC ninja, HW hacker w/ FPGA hammer.
Lafayette, Indiana
John Lee
johnteee
Senior FullStack & App Developer;
Web,Android,iOS;
Java,ES6,Golang,Kotlin,Swift,Rust;
Laravel,Vuejs,Gin;
Docker;
FP;
Taipei
José Moreira
cusspvz
Software Architecture, Security and Infrastructure | Open-Source <3
mosano.eu Póvoa de Varzim, Porto, Portugal