A minimal GPU design in Verilog to learn how GPUs work from the ground up

Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

A Verilog synthesis flow for Minecraft redstone circuits

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

A Linux-capable RISC-V multicore for and by the world

BaseJump STL: A Standard Template Library for SystemVerilog

The root repo for lowRISC project and FPGA demos.

Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.

A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.

Naive Educational RISC V processor

Simple hash table on Verilog (SystemVerilog)