Skip to content
View r-rathi's full-sized avatar

Block or report r-rathi

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Maximum 250 characters. Please don't include any personal information such as legal names or email addresses. Markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse
4 stars written in SystemVerilog
Clear filter

A minimal GPU design in Verilog to learn how GPUs work from the ground up

SystemVerilog 8,989 702 Updated Aug 18, 2024

Verilator open-source SystemVerilog simulator and lint system

SystemVerilog 3,243 728 Updated Dec 19, 2025

Verilog-Mode for Emacs with Indentation, Hightlighting and AUTOs. Master repository for pushing to GNU, verilog.com and veripool.org.

SystemVerilog 279 98 Updated Nov 8, 2025

SystemVerilog Extension Library -- a library of utilities for generic programming and increased productivity

SystemVerilog 33 6 Updated Jul 27, 2024