Replies: 15 comments 3 replies
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I am the one workint on everything. Can you share samples so i can give it a try? |
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just added the missing EM_TI definitions in the elf parser so you dont have to -a tms320 by hand now in git master |
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about the endianness this is defined with those are variants of the tms320 disassembler. i dont think theres a way to force 16 or 32 bit, and i think the endianness is ignored in the current plugin, shouldnt take more than 1 line of code to fix that. ill look into that to get the same output as in the right panel. but seems like the capstone implementation needs some work to get there. this is how it looks in r2 from git now after my fixes |
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Only one line correct disassembly :( Thank you for your help. I have tried to find the tables for the capstone plugin but i am not shure if i found the correct files and what i have found looks difficult (with my limited experience). |
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with some more fixes i got this. but i think now it's up to capstone not handling compact instructions well for c64x. ill look into that to report whatever is needed there too |
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can i use this sample.out in the testsuite? |
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in capstone i filled the following tickets: |
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Yes, it is made with ti ccs from an empty main. Should be a good file for tests. You work with incredible speed. |
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thanks |
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added test. also waiting for this pr to be merged in capstone to update the dependency in r2 and continue pushing to get compact mode implemented capstone-engine/capstone#2648 |
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as an update: capstone fixed the endian bug, but they dont support compact instructions yet. maybe we shuold update our copy. but i have too much open fronts to handle that, can you follow up in the capstone repo? |
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I will subscribe to the cpstone issues. |
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I have compiled the radare with git version. But then i found a strange output. Ti dis6x: radare (with big endian =1): So i think a4 = a4 does not make sense... Unfortunately the chain is complicated.
Something for experts with special skills ;) Thank you for your help to this point. |
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hold on. i will integrate the GNU disassembler, that should be correct as long as its the one used by GCC and that's kind of a standard toolchain for that arch. is there any other free/open alternative? |
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Unfortunately I don't know of any open tool as a disassembler for this CPU series |
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initial work done here #24139 can u contribute to it after merged? |
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Is someone working with the arch=tms320 disassembler?
I am playing around with it but not able to get any sensfull disassembly.
It looks like the byte order is wrong and the the instructions are handled wrong in some byte or 3 byte instructions while the tms320 has 32 bit or 16 bit instructions only.
Is there a parameter to change the byte order?
Can 16bit and 32bit instruction decoding be forced?
ELFDATA2LSB may be the needed parsing.
I am using radare2 on Windows.
radare2 5.9.8 1 @ windows-x86-64
birth: git.5.9.8 Tue 11/19/2024__11:46:03.42
commit: 4eb49d5
options: gpl -O? cs:5 cl:1 meson
This is a comparision of the radare2 output and the ti disassembler dis6x.exe, showing the wrong instruction byte order and the incorrect instruction length.
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