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Zynq UltraScale PS driving data into 2 AXI FIFOs instantiated in PL fabric, via 2 DMAs instantiated in PL fabric.
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I Implemented from scratch the AXI DMA loopback with AXI4-Stream Data FIFO and proved the h/w design is working successfully with Vitis C code from Xylinx Standard Example.
Tcl UpdatedSep 15, 2025 -
my work on RFSoc4*2 FPGA
1 UpdatedSep 11, 2025 -
AWShosted_ecommerce_app_with_LLMChatbot Public
Forked from the-cloud-bootcamp/acw-en-projectaws create ecommerce appli with docker, aws lightsail and openrouter, chatbot LLM with selecting backend ML models like deepseek/claude
CSS UpdatedJul 15, 2025 -
torvalds_linux Public
Forked from torvalds/linuxLinux kernel source tree
C Other UpdatedJun 1, 2025 -
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Linux_Driver_Tutorial_legacy_fork Public
Forked from Johannes4Linux/Linux_Driver_Tutorial_legacyA Tutorial how to get started with Linux Kernel Modules and Linux Drivers.
C The Unlicense UpdatedJul 15, 2024 -
BBB-BareMetal Public
Forked from allexoll/BBB-BareMetalWorks on the beaglebone black (bare metal)
C MIT License UpdatedApr 29, 2024 -
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rpi-networklab Public
Forked from hpreston/rpi-networklablinux Nw lab setups using RPI
UpdatedMar 4, 2022 -
MeltdownDemo Public
Forked from SamuelXing/MeltdownDemoMeltdown attack demo.
C UpdatedFeb 25, 2018
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