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392 lines (377 loc) · 14.2 KB
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#include "nv_rend.h"
#include <string_view>
// for sv literals
using namespace std::string_view_literals;
// generated with script/pal.pl -C
#include "lat.inc"
int NV_renderer::check_lat_set(const NV_sorted *ns) const {
int res = 0;
std::unordered_set<std::string_view> visited;
for ( auto &nitem: *ns ) {
auto fi = s_lats.find(nitem.first);
if ( fi == s_lats.cend() ) {
fprintf(m_out, "LMissed: %.*s\n", (int)nitem.first.size(), nitem.first.data());
res++;
} else {
visited.insert(nitem.first);
}
}
// dump unvisited
for ( auto &li: s_lats ) {
auto fi = visited.find(li.first);
if ( fi != visited.cend() ) continue;
fprintf(m_out, "LUnk: %.*s\n", (int)li.first.size(), li.first.data());
}
return res;
}
template <typename T>
static bool check_kv(const NV_extracted &kv, const char *what, T val) {
auto ki = kv.find(what);
if ( ki == kv.cend() ) return false;
return (T)ki->second == val;
}
static bool check_zero_kv(const NV_extracted &kv, const char *what) {
auto ki = kv.find(what);
if ( ki == kv.cend() ) return false;
return !ki->second;
}
static bool check_nonzero_kv(const NV_extracted &kv, const char *what) {
auto ki = kv.find(what);
if ( ki == kv.cend() ) return false;
return ki->second;
}
inline static bool has_key(const NV_extracted &kv, const char *what) {
auto ki = kv.find(what);
return ki != kv.end();
}
inline static bool check_pred(const struct nv_instr *ins, const NV_extracted &kv, const std::string_view &what, uint64_t &val) {
auto pi = ins->predicated->find(what);
if ( pi == ins->predicated->end() ) return false;
val = pi->second(kv);
return true;
}
/* I suspect that latency tables *_2.txt are too convervative for some instructions comparing with c8.txt
For example there is IMAD with value 4 and IMAD.WIDE with value 9
In _2.txt IMAD included in many groups but none reflect 'wide', like
IMAD_OP = {IMAD,IMADfmalighter_pipe,IMAD32I,IMAD32Ifmalighter_pipe,
IMUL,IMULfmalighter_pipe,IMUL32I,IMUL32Ifmalighter_pipe}
row in RaW looks like IMAD_OP`{Rd @RdRange,Rd2 @Rd2Range} : 5 4 6 6 6 6 8 6 6 7 7 7 7 7 7 6 4
So I add -S option to dg2.pl to collect most frequently patched instructions
This method is quick and dirty hack to relax delays for some instruction - sure it is incomplete
and knows only some most popular. All return values were borrowed from c8.txt - check that they
are not less than the minimum value in TABLE_TRUE corresponding row
*/
std::optional<int> NV_renderer::relax_latency(const struct nv_instr *ins, const NV_extracted &kv) const {
std::string_view iname = ins->name;
std::string_view iclas = ins->cname;
std::optional<int> res;
switch( ins->name[0] ) {
case 'I': // IMAD, IMNMX, ISETP & IMUL(32I)
if ( iname == "IMAD"sv ) {
if ( !iclas.starts_with("imad_hi") && !iclas.starts_with("imad_wide") ) res.emplace(4);
} else if ( iname == "IMUL"sv ) {
if ( !iclas.starts_with("imul_wide") ) res.emplace(4);
} else if ( iname == "IMUL32I"sv ) {
if ( !iclas.starts_with("imul32i_wide") ) res.emplace(7);
} else if ( iname == "IMNMX"sv ) {
if ( !iclas.starts_with("imnmx_64") ) res.emplace(5);
} /* else if ( iname == "ISETP"sv ) {
if ( !iclas.starts_with("isetp_64") ) res.emplace(5);
} */
break;
case 'S': // SEL
if ( iname == "SEL"sv ) {
uint64_t dsize = 0;
if ( check_pred(ins, kv, "IDEST_SIZE"sv, dsize) && 64 != dsize ) res.emplace(3);
}
break;
case 'U': // UIADD3, UIMNMX, UISETP, UMOV & USEL both 4
if ( iname == "UIADD3"sv ) {
if ( !iclas.starts_with("uiadd3_64") ) res.emplace(6);
} else if ( iname =="UIMNMX"sv ) { // sm120 only?
if ( !iclas.starts_with("uimnmx_64") ) res.emplace(6);
} /* else if ( iname =="UISETP"sv ) { // sm120 only?
if ( !iclas.starts_with("uisetp_64") ) res.emplace(6);
} */ else if ( iname == "UMOV"sv || iname == "USEL"sv ) {
uint64_t dsize = 0;
if ( check_pred(ins, kv, "IDEST_SIZE"sv, dsize) && 64 != dsize ) res.emplace(4);
}
break;
}
return res;
};
// delay plop3 typically looks like
// PLOP3.LUT P0,PT,PT,PT,PT, 0x80, 0 ?trans2 ; LUT 80: a & b & c
// this is class plop3_lut_2out_ and has predicates names Pv, Pp, Pq, Pr
// another forms with 4 predicates:
// - class plop3_lut_2out_uniform_ with Pv, Pp, Pq & Upr
// - class uplop3_lut_2out_ with UPv, UPp, UPq, UPr
bool NV_renderer::delay_plop(const struct nv_instr *ins, const NV_extracted &kv) const {
std::string_view iclas = ins->cname;
auto check_pr = [&kv](const std::string_view &what) -> bool {
auto ki = kv.find(what);
if ( ki == kv.end() ) return false;
return ki->second == 7; // both Predicate & UniformPredicate marked 7 as (U)PT
};
if ( iclas == "plop3_lut_2out_"sv ) {
constexpr std::array preds = { "Pv"sv, "Pp"sv, "Pq"sv, "Pr"sv };
return std::all_of(preds.cbegin(), preds.cend(), check_pr);
}
if ( iclas == "plop3_lut_2out_uniform_"sv ) {
constexpr std::array preds = { "Pv"sv, "Pp"sv, "Pq"sv, "UPr"sv };
return std::all_of(preds.cbegin(), preds.cend(), check_pr);
}
if ( iclas == "uplop3_lut_2out_"sv ) {
constexpr std::array preds = { "UPv"sv, "UPp"sv, "UPq"sv, "UPr"sv };
return std::all_of(preds.cbegin(), preds.cend(), check_pr);
}
return false;
}
static const std::unordered_map<std::string_view, int> s_spec9 = {
{ "UTCCP"sv, 10 },
{ "UTCHMMA"sv, 12 },
{ "UTCIMMA"sv, 12 },
{ "UTCMXQMMA"sv, 14 },
{ "UTCOMMA"sv, 12 },
{ "UTCQMMA"sv, 12 },
{ "UTCSHIFT"sv, 13 },
};
static const std::unordered_map<std::string_view, int> s_spec12 = {
{ "UIMNMX"sv, 9 },
{ "UISETP"sv, 9 },
{ "UMEMSETS"sv, 11 },
{ "USEL"sv, 7 }
};
std::optional<int> NV_renderer::calc_latency(const struct nv_instr *ins, const NV_extracted &kv) const {
std::string_view iname = ins->name;
std::string_view iclas = ins->cname;
std::optional<int> res;
// pre-classify - rename some opcodes
switch( ins->name[0] ) {
case 'A': if ( iname == "AL2P"sv ) {
/* AL2P has only 2 form:
- NonZeroRegister:Ra ',' SImm(11)*:Ra_offset - class al2p__RaNonRZ
- ZeroRegister("RZ"):Ra ',' UImm(10)*:Ra_offset - class al2p__RaRZ
so I guessed that _INDEXED is first one
*/
if ( iclas != "al2p__RaRZ"sv ) iname = "AL2P_INDEXED"sv;
}
break;
case 'V': if ( iname == "VOTE_VTG"sv ) iname = "VOTE"sv; // bcs VOTE_VTG is just alt alias
break;
}
// check in s_lats
auto li = s_lats.find(iname);
if ( li == s_lats.end() ) return res;
// check that we have value (can be missed for bad states
if ( li->second.first ) {
res.emplace(li->second.first);
if ( !li->second.second ) // if no state for post-processing - we are done
return res;
}
// post-processing - keep them in sorted order for better navigation
switch(li->second.second) {
case LatSpecial::Spec1: // !*64
if ( !iclas.starts_with("f2i_Rd64"sv) && !iclas.ends_with("64b"sv) ) res.emplace(13);
break;
case LatSpecial::Spec2: // !F64
// frnd f64 has fmt /F64ONLY - 15
if ( iname == "FRND"sv ) {
if ( !check_kv(kv, "fmt", 15) ) res.emplace(14);
break;
}
// check f2f & i2f
if ( iclas.starts_with("f2f_f64"sv) ) break;
if ( iclas.starts_with("i2f_Rd64"sv) ) break;
res.emplace(13);
break;
case LatSpecial::Spec3: // with Rb (and I guess with URb too)
if ( has_key(kv, "Rb") || has_key(kv, "URb") ) {
// NANOSLEEP: 19
// NANOTRAP: 18
// WARPSYNC: 18
if ( iname == "NANOSLEEP"sv ) res.emplace(19);
else res.emplace(18);
}
break;
case LatSpecial::Spec4: // .168128 - 11 .168256 - 11 .88128 - 10
{ auto ki = kv.find("size");
if ( ki == kv.cend() ) break;
if ( !ki->second ) res.emplace(10); // 88128 == 0
else res.emplace(11);
}
break;
case LatSpecial::Spec5:
// .16816.F16.* - 16
// .1688.F16.* - 15
// .F32.{16816.F16|16816.E8M7|1688.E8M10} - 42
// .F32.{1684.E8M10|1688.F16|1688.E8M7} - 40
// .SP.16816.F16.* - 19
// .SP.16832.F16.* - 19
// .SP.F32.{16816.E8M10|16832.F16|16832.E8M7} - 46
// .SP.F32.{16816.F16|16816.E8M7|1688.E8M10} - 45
{
bool has_sp = false;
auto ki = kv.find("sp");
if ( ki != kv.cend() ) has_sp = true;
// first 'size', second 'dstfmt'
bool f32 = false;
ki = kv.find("dstfmt");
if ( ki != kv.cend() && ki->second ) f32 = true;
ki = kv.find("size");
if ( ki == kv.cend() ) break;
if ( !f32 ) {
// 16816 - 1
if ( 1 == ki->second ) { res.emplace(has_sp ? 19: 16); break; }
// 1688 - 0
if ( !ki->second ) { res.emplace(15); break; }
// 16832 - 3
if ( has_sp && 3 == ki->second ) { res.emplace(19); break; }
} else {
// 1684 - 2
if ( ki->second == 2 || !ki->second ) { res.emplace(has_sp ? 45: 40); break; }
else { res.emplace(has_sp ? 46: 42); break; }
}
}
break;
case LatSpecial::Spec6: // .16816 - 10 .16832 - 10 .SF - 7 .SF.SP 10 .SP.16832 - 13 .SP.16864 - 13
{ bool sfonly = false;
bool sponly = false;
auto ki = kv.find("sf");
if ( ki != kv.cend() ) sfonly = true;
ki = kv.find("sp");
if ( ki != kv.cend() ) sponly = true;
if ( sfonly && sponly ) { res.emplace(10); break; } // .SF.SP
if ( sfonly ) { res.emplace(7); break; } // .SF
ki = kv.find("size"); // SIZE_16816_16832
if ( ki == kv.cend() ) break;
if ( 0 == ki->second ) res.emplace(10); // 16816
else if ( 1 == ki->second ) res.emplace(sponly ? 13 : 10); // 16832
else if ( 2 == ki->second ) res.emplace(13); // 16864
}
break;
case LatSpecial::Spec7: // .16816 - 10 .1684 - 9 .1688 - 9
{ auto ki = kv.find("size"); // DMMA_SIZE
if ( ki == kv.cend() ) break;
if ( 3 == ki->second ) res.emplace(10); // 16x8x16 == 3
else if ( ki->second ) res.emplace(10); // 16x8x8 - 2, 16x8x4 - 1
}
break;
case LatSpecial::Spec8:
if ( iclas.starts_with("utcbar_flush") ) res.emplace(17);
else res.emplace(11); // both 1cta & 2cta have the same value
break;
case LatSpecial::Spec9: {
auto i9 = s_spec9.find(iname);
if ( i9 != s_spec9.cend() ) {
res.emplace(i9->second);
}
}
break;
case LatSpecial::Spec10: // rpcmov
if ( iclas.starts_with("rpcmov_src") ) res.emplace(14);
else if ( has_key(kv, "sz") ) res.emplace(9); // both 32 & 64 have the same value
break;
case LatSpecial::Spec25:
case LatSpecial::Spec11: res.emplace(7);
break;
case LatSpecial::Spec12: { // .64 - sm120 only?
auto ki = kv.find("fmt");
if ( ki == kv.cend() ) break;
if ( ki->second < 2 ) break; // 0 - u32, 1 - s32
auto i12 = s_spec12.find(iname);
if ( i12 != s_spec12.cend() ) res.emplace(i12->second);
}
break;
case LatSpecial::Spec18: // WARPGROUP: 16 16 14
if ( iclas.starts_with("warpgroup_wait"sv ) ) res.emplace(14);
else res.emplace(16);
break;
case LatSpecial::Spec20: // bpt
if ( iclas == "bpt__onlyDRAIN"sv ) res.emplace(9);
else if ( iclas == "bpt__WAIT"sv ) res.emplace(9); // there is no PAUSE
break;
case LatSpecial::Spec21: { // MUFU
// EX2@.EX2.{F16x2, BF16x2}@.RCP@.RSQ@.TANH
// 8 24 8 8 9
auto ki = kv.find("mufuop");
if ( ki == kv.cend() ) ki = kv.find("mufu");
if ( ki == kv.cend() ) break;
if ( 4 == ki->second || 5 == ki->second ) // 4 - RCP. 5 - RSQ
res.emplace(8);
else if ( 9 == ki->second ) // 9 - TANH
res.emplace(9);
else if ( 2 == ki->second ) { // 2 - EX2
if ( iclas.starts_with("mufu_fp16"sv ) ) // I have zero ideas where else extract F16/BF16
res.emplace(24);
else res.emplace(8);
}
}
break;
case LatSpecial::Spec22: // .F32
if ( iclas.starts_with("hadd2_F32") ) res.emplace(9);
break;
case LatSpecial::Spec23: // .FINAL
if ( iclas == "out__FINAL"sv ) res.emplace(9);
break;
case LatSpecial::Spec24: // .FLUSH
if ( check_nonzero_kv(kv, "flush") ) res.emplace(15);
break;
case LatSpecial::Spec26: // .GSB - sm90 only?
if ( check_zero_kv(kv, "gsb") ) res.emplace(9);
break;
case LatSpecial::Spec27: // IMAD
// .HI - 7
// .WIDE - 9
// .WIDE.READ.AB - 17
// .WIDE.READ.CH - 17
// .WIDE.READ.CL - 17
// .WIDE.WRITE.DH - 18
// .WIDE.WRITE.DL - 18
if ( iclas.starts_with("imad_hi_x") ) res.emplace(17);
else if ( iclas.starts_with("imad_hi") ) res.emplace(18);
else if ( iclas.starts_with("imad_wide") ) res.emplace(9);
break;
case LatSpecial::Spec28: // .IMM
if ( has_key(kv, "sImm") ) res.emplace(7);
break;
case LatSpecial::Spec29: // .RELEASE - I guess stands for dealloc
if ( iclas.ends_with("dealloc") ) res.emplace(18);
break;
case LatSpecial::Spec31: // .SP
if ( iclas.starts_with("qmma_sp"sv) ) res.emplace(7);
break;
case LatSpecial::Spec32: // .SP.{168128.*|16864.*8.*8} - 30
// .SP.{16832.*|16864.*4.*4} - 29
// .SP.{8832.*|8864.*} - 23 - wtf?
// .{16816.*|16832.*4.*4} - 26
// .{16832.*8.*8|16864.*} - 26
// .{8816.*|8832.*} - 20
{
bool has_sp = false;
auto ki = kv.find("sp");
if ( ki != kv.cend() ) has_sp = true;
ki = kv.find("size");
if ( ki == kv.cend() ) break;
// 4 - 16816, 5 - 16832, 6 - 16864
if ( ki->second == 6 ) { res.emplace( has_sp ? 30 : 26 ); break; }
else if ( ki->second == 5 ) { res.emplace( has_sp ? 29 : 26); break; }
else if ( ki->second == 4 ) { res.emplace(26); break; }
else if ( ki->second == 3 ) { res.emplace( has_sp ? 29 : 26); break; } // 3 - 16832
else if ( !ki->second ) { res.emplace(20); break; } // 0 - 1688
}
break;
case LatSpecial::Spec33: // .SYNC.DEFER_BLOCKING
if ( check_nonzero_kv(kv, "defer_blocking") ) res.emplace(23);
break;
case LatSpecial::Spec34: // .WIDE
if ( check_nonzero_kv(kv, "wide") ) {
// IMUL: 9
// IMUL32I: 12
if ( iname == "IMUL"sv ) res.emplace(9);
else if ( iname == "IMUL32I"sv ) res.emplace(12);
}
break;
}
return res;
}