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Lock-free MPSC channel in Zig achieving 50+ billion messages/second via ring-decomposed architecture

Zig 141 10 Updated Dec 19, 2025

A double-to-string conversion algorithm based on Schubfach and yy

C++ 157 10 Updated Dec 22, 2025

SRAM project for GF180MCU - created from wafer-space template

Python 1 Updated Dec 16, 2025

Simple starter project for Hardcaml development

OCaml 19 3 Updated Dec 2, 2025

Fast and Furious AMD Kernels

C++ 325 40 Updated Dec 19, 2025

RISC-V out-of-order core for education and research purposes

Python 81 21 Updated Dec 8, 2025

Domain-specific language designed to streamline the development of high-performance GPU/CPU/Accelerators kernels

C++ 4,274 350 Updated Dec 22, 2025

GateMate's PHY Interface for PCI Express (PIPE)

Verilog 4 Updated Dec 17, 2025

TCP Offload Engine

Verilog 76 32 Updated Nov 18, 2017

🥧 Savoury implementation of the QUIC transport protocol and HTTP/3

Rust 11,057 908 Updated Dec 20, 2025

A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration.

Verilog 436 104 Updated Dec 2, 2019

A robust, open-source physical layer implementation for FPGA-to-FPGA communication over high-speed serial links.

SystemVerilog 20 3 Updated Dec 21, 2025

RV4028 - A hackable Risc-V computer

Verilog 5 Updated Oct 31, 2025

wafer.space online platform

Python 3 Updated Dec 18, 2025

55nm CMOS Open Source PDK by ICsprout Integrated Circuit Co., Ltd.

Verilog 143 17 Updated Dec 17, 2025

FPGA based WiFi Intrusion detection system

VHDL 36 7 Updated Dec 15, 2025

A low-overhead dynamic binary instrumentation and modification tool for ARM (both AArch32 and AArch64 support) and RISC-V (RV64GC).

C 388 73 Updated Jan 21, 2025

Artifact for paper "PIM is All You Need: A CXL-Enabled GPU-Free System for LLM Inference", ASPLOS 2025

Python 113 19 Updated May 3, 2025

RISC-V Zve32x Vector Coprocessor

Assembly 195 56 Updated Dec 2, 2023

A machine learning accelerator core designed for energy-efficient AI at the edge.

Emacs Lisp 1,954 214 Updated Dec 19, 2025

PCIe Endpoint on Xilinx 7-Series FPGAs with the PCIE_2_1 hard block and GTP transceivers

Verilog 64 7 Updated Apr 27, 2025

Full-throttle, wire-speed hardware implementation of Wireguard VPN, using low-cost Artix7 FPGA with opensource toolchain. If you seek security and privacy, nothing is private in our codebase. Our d…

Verilog 1,292 31 Updated Dec 21, 2025

BSD licensed YM2413/VRC-7 cycle-accurate core

Verilog 24 3 Updated Jan 4, 2025

A collection of array rotation algorithms.

C 162 9 Updated Jan 3, 2023

Parrot is a C++ library for fused array operations using CUDA/Thrust. It provides efficient GPU-accelerated operations with lazy evaluation semantics, allowing for chaining of operations without un…

Cuda 240 14 Updated Dec 18, 2025

A novel data compression framework

C 2,854 122 Updated Dec 22, 2025

An FPGA-based mechanical keyboard with an integrated USB hub and communication interfaces

VHDL 197 7 Updated Dec 15, 2025

RTL logic synthesis

C++ 123 3 Updated Oct 16, 2025

A fast framework for writing baseline compiler back-ends in C++

LLVM 596 29 Updated Dec 12, 2025
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