opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

Open source FPGA-based NIC and platform for in-network compute

RTL, Cmodel, and testbench for NVDLA

SERV - The SErial RISC-V CPU

Verilog library for ASIC and FPGA designers

An open source GPU based off of the AMD Southern Islands ISA.

Enabling Flexible FPGA High-Level Synthesis of Tensorflow Deep Neural Networks

RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)

RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT

XCrypto: a cryptographic ISE for RISC-V

Using VexRiscv without installing Scala