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Starred repositories

6 results for source starred repositories written in Verilog
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OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

Verilog 2,328 749 Updated Dec 17, 2025
Verilog 1,819 415 Updated Dec 15, 2025

A small, light weight, RISC CPU soft core

Verilog 1,489 177 Updated Dec 8, 2025

Z80 open-source silicon clone. Goal is to become a silicon proven, pin compatible, open-source replacement for classic Z80.

Verilog 708 31 Updated Dec 15, 2025

A tiny Open POWER ISA softcore written in VHDL 2008

Verilog 707 109 Updated Dec 14, 2025

Open source retro ISA video card

Verilog 547 30 Updated Oct 24, 2024