EDA wiki

SystemVerilog compiler and language services

Verilator open-source SystemVerilog simulator and lint system

Chisel: A Modern Hardware Design Language

Python-based Hardware Design Processing Toolkit for Verilog HDL

XLS: Accelerated HW Synthesis

(WIP) Open-source Rust gate-level EDA infrastructure: parsers and databases

Circuit IR Compilers and Tools

Yosys Open SYnthesis Suite

Intermediate Language (IL) for Hardware Accelerator Generators

Icarus Verilog

A hardware compiler based on LLHD and CIRCT

Low Level Hardware Description — A foundation for building hardware design tools.

Test suite designed to check compliance with the SystemVerilog standard.

A modern hardware definition language and toolchain based on Python

An awesome list of e-graph resources