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Highlights
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Lists (20)
algorithm discovery
SOTA algorithm discovery based on LLMs.1 repository
alu
Arithmetic logic unit, for verification purpose (may later for PPA opt.).17 repositories
courses
course materials.1 repository
decision-making
some solvers, heuristics, etc.1 repository
EDA
eda infra.18 repositories
formal
formal techniques21 repositories
hardware trojan
Hardware trojan detection3 repositories
HLS
8 repositories
LLM Agents
16 repositories
LLM Code
14 repositories
LLM Inference
7 repositories
LLMs
15 repositories
mlir
use of mlir.8 repositories
Parser
10 repositories
Program Representation
8 repositories
RISC-V
7 repositories
Scale
1 repository
simu/emu
some simulation/emulation tech.3 repositories
synthesis
12 repositories
verification
list for hardware verification79 repositories
Starred repositories
This repository includes the data and scripts utilized in the study titled "Improving LLM-based Verilog Code Generation with Data Augmentation and RL (DATE25)".
Research paper based on or related to ABC.
PolyBench/C benchmark suite (version 4.2.1 beta) from http://web.cse.ohio-state.edu/~pouchet/software/polybench/
A Large-Scale, Open-Source Dataset for High-Level Synthesis
Tongyi Deep Research, the Leading Open-source Deep Research Agent
A minimal tensor processing unit (TPU), inspired by Google's TPU V2 and V1
2025 OpenHW submission for accelerating Boolean Satisfiability on FPGA
CLEVER: Code Lean Evaluation for Verified End-to-end Reasoning
Verified graph rewriting (for dataflow circuits).
Binary Single Precision Floating-point Fused Multiply-Add Unit Design (Verilog HDL)
Fully synthesizable and paramterizable, IEEE-754 compliant Floating Point Unit (FPU) in systemverilog. Supports fused multiply add, division and square root operations.
Paper2Code: Automating Code Generation from Scientific Papers in Machine Learning
FSA: Fusing FlashAttention within a Single Systolic Array
A modern hardware definition language and toolchain based on Python
Introduction to MLIR and xDSL training course
Tactics for discharging Lean goals into SMT solvers.
Lean 4 programming language and theorem prover
Experiments on automation for Lean
Test suite designed to check compliance with the SystemVerilog standard.