SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

port from python to C++ PyVCD lib

A parser for Value Change Dump (VCD) files as specified in the IEEE System Verilog 1800-2012 standard.

VCD (Value Change Dump) Tracing for C++

Coriolis VLSI EDA Tool (LIP6)

VCD file (Value Change Dump) command line viewer

Tool to convert a ascii-dump layout from Cadence Virtuoso 5.1 to a svg

AMBA bus generator including AXI4, AXI3, AHB, and APB

Deep learning toolkit-enabled VLSI placement

Cell library characterizer

Synopsys Verdi applet that presents a view of the source code running on a RISC-V processor with a simulation waveform.