SystemVerilog file list pruner

A machine learning accelerator core designed for energy-efficient AI at the edge.

VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!

Curriculum for a university course to teach chip design using open source EDA tools

SystemVerilog language-oriented exercises

Tranining Completion Project : : Verification of AXI Direct Memory Access (DMA) using UVM

A repository aggregating links to essential documentation, tutorials, and research papers for hardware Design Verification.

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

Contains the code examples from The UVM Primer Book sorted by chapters.

Welcome to the 108 RTL Projects repository! This collection aims to provide a comprehensive set of RTL design projects ranging from simple digital circuits to complex system designs. , you'll find …

a collection of cv and resume styles

Open source ISS and logic RISC-V 32 bit project

Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

Verilog I2C interface for FPGA implementation

openMSP430 project ported to Terasic DE0 and DE0CV. (I2C master core and basic UART included)

Verification IP for I2C protocol

A (simple) C/C++ simulator for a (simple) RISC-V CPU

training labs and examples

Reference examples and short projects using UVM Methodology

This is the repository for the IEEE version of the book

This is the main repository for all the examples for the book Practical UVM

Verilog PCI express components

A List of Free and Open Source Hardware Verification Tools and Frameworks

A library to generate LaTeX expression from Python code.

This verfication intellectual property for axi-4 protocol

This is normal basic UVM testbench for AMBA Bridge AHB_APB

List of Computer Science courses with video lectures.

Envision a future where every student can read all the code of a teaching operating system.