GPL v3 2D/3D graphics engine in verilog

The Zylin ZPU

The A2I core was used as the general purpose processor for BlueGene/Q, the successor to BlueGene/L and BlueGene/P supercomputers

High level Data Link Layer Control (HDLC) Protocol (16 bit) implementation using VHDL hardware description language.

RCA COSMAC CDP1802 functional equivalent CPU core in VHDL

GPIB IEEE 488.1 core

IEEE-488 (GP-IB, HP-IB) synthesizable core in VHDL

VHDL 1802 Core with TinyBASIC for the Lattice MachXO2 Pico board