Blocks & Bots: An Open Chip Playground augmented with LLMs. Please check: https://sscs.ieee.org/technical-committees/tc-ose/sscs-pico-design-contest/

Spike, a RISC-V ISA Simulator

RISC-V Verification Interface

Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.

SystemVerilog for ASIC/FPGA Design & Simulation, with Synopsys Tool Flow

A Python 3 ncurses tool to facilitate grading student submissions on the zyBooks online programming system

A Python 3 ncurses tool to facilitate grading student submissions on the zyBooks online programming system

Python script to transform a VCD file to wavedrom format

RV-Debugger-BL702 Project, an opensource debugger implement

Working Draft of the RISC-V Debug Specification Standard

Python Cache Hierarchy Simulator

A simplified cache simulator for instructional purposes

A HDMI Compatible PMOD for the ArtyA7 (and probably others) FPGA Dev Board

CORE-V Family of RISC-V Cores

The 30 Days of Python programming challenge is a step-by-step guide to learn the Python programming language in 30 days. This challenge may take more than 100 days. Follow your own pace. These vide…

Fast and memory-efficient exact attention

PDK installer for open-source EDA tools and toolchains. Distributed with setups for the SkyWater 130nm and Global Foundries 180nm open processes.

IIC-OSIC-TOOLS is an all-in-one Docker image for SKY130/GF180/IHP130-based analog and digital chip design. AMD64 and ARM64 are natively supported.

Fork of OpenOCD that has RISC-V support

TestFloat release 3

Small portable AES128/192/256 in C

LibTomCrypt is a fairly comprehensive, modular and portable cryptographic toolkit that provides developers with a vast array of well known published block ciphers, one-way hash functions, chaining …

SystemVerilog compiler and language services

RISC-V cryptography extensions standardisation work.

GNU toolchain for RISC-V, including GCC

EE 628: Analysis and Design of Integrated Circuits (University of Hawaiʻi at Mānoa)

Generates an implication chart to minimise a finite state machine