under construction... 🚧

The audio player software for psoc-soc

PSOC SoC code with peripherals and synthesis scripts for FPGA/ASIC

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Utility blocks for the Wishbone interface

IEEE 754 single precision floating point library in systemverilog and vhdl

VHDL examples and tutorial based on GateMateA1-EVB board

PCIe (1.0a to 2.0) Virtual Root Complex model for Verilog, with Endpoint capabilities

UART Co-Emulation Example

BetterBahn is an open-source project that aims to improve the train travel experience in germany. The current focus is on split-ticketing. However, further functions are planned to follow in the fu…

GDB server stub for replaying recorded HDL simulations

wellen: waveform datastructures in Rust. Fast VCD, FST and GHW parsing for waveform viewers.

An Embassy HAL for the RISCV-based NEORV32 SoC/microcontroller

Scripts to build a trimmed-down Windows 11 image.

This task group will propose ISA extension(s) and non-ISA hardware and software interop interfaces to enable routine reuse and composition of a subcategory of custom extensions called composable ex…

Branch with Immediate (Zibi) Ratification Plan

OSVVM UART Verification Components. Uart Transmitter with error injection for parity, stop, and break errors. UART Receiver verification component with error handling for parity, stop, and break er…

A windows console application for serial communications.

AMD Open Hardware Design Competition 2025 Contribution: SNN-based Smart Watchdogs for RISC-V Fault Detection

Package manager and build system for VHDL, Verilog, and SystemVerilog

Verilog for a SECDED Hsaio ECC and a DEC ECC. Power, delay, and area are compared for Berkeley MASIC EEW241B - Advanced Digital Integrated Circuits.

Implementation of the PRINCE lightweight block cipher in VHDL.

Baseband Receiver IP for GPS like DSSS signals

Checks for EDA tools supporting VHDL-2008 and VHDL-2019.

Command-line tool from the Alire project and supporting library

A Risc-V SoC for Tiny Tapeout

Efinix T20Q100 Low Cost Development Board

A simple design showing the NeoRV32 executing code from an LSRAM in the FPGA to drive PWM and UART