XiangShan (香山) is an open-source high-performance RISC-V processor project.

中文说明在此。

XiangShan's documentation is available at docs.xiangshan.cc.

XiangShan Design Docuemtn for Kunminghu V2R2 has been published separately. You can find it at docs.xiangshan.cc/projects/design.

XiangShan User Guide has been published separately. You can find it at docs.xiangshan.cc/projects/user-guide or XiangShan-User-Guide/releases.

We are using Weblate to translate documentation into English and other languages. Your contributions are welcome—come and help us improve it!

All XiangShan documents are licensed under the CC-BY-4.0.

Our paper introduces XiangShan and the practice of agile development methodology on high performance RISC-V processors. It covers some representative tools we have developed and used to accelerate the chip development process, including design, functional verification, debugging, performance validation, etc. This paper is awarded all three available badges for artifact evaluation (Available, Functional, and Reproduced).

Paper PDF | IEEE Xplore | BibTeX | Presentation Slides | Presentation Video

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The first stable micro-architecture of XiangShan is called Yanqihu (雁栖湖) and is on the yanqihu branch, which has been developed since June 2020.

The second stable micro-architecture of XiangShan is called Nanhu (南湖) and is on the nanhu branch.

The current version of XiangShan, also known as Kunminghu (昆明湖), is still under development on the master branch.

The micro-architecture overview of Kunminghu (昆明湖) is shown below.

Some of the key directories are shown below.

git clone https://github.com/OpenXiangShan/XiangShan.git
cd XiangShan/
export NOOP_HOME=$(pwd)
#复位到指定ID，以及改相关硬件
git reset --hard xxxxxx
make init
#dramsim3目前可以使用我的或者自己编，单双通道可在运行时配置
python3 ./scripts/xiangshan.py --build --dramsim3 /nfs/home/zhangyuxin/spec_test/0218_spec_test/DRAMsim3 --with-dramsim3 --threads 16 --config KunminghuV2Config
#xiangshan_DDR4_8Gb_x8_3200_1ch_xmp为单通道，xiangshan_DDR4_8Gb_x8_3200_2ch_xmp为双通道
./build/emu --dramsim3-ini /nfs/home/zhangyuxin/spec_test/0218_spec_test/DRAMsim3/configs/xiangshan_DDR4_8Gb_x8_3200_1ch_xmp.ini --no-diff -i /nfs/home/zhangyuxin/temp/am_temp/am_new_for_pldm/nexus-am/apps/mem_test/mem_test_bw/build/mem_test_bw-riscv64-xs.bin >latency.log 2> perf.log

make bsp

make idea

• Run make verilog to generate verilog code. This generates multiple .sv files in the build/rtl/ folder (e.g., build/rtl/XSTop.sv).
• Refer to Makefile for more information.

• Set environment variable NEMU_HOME to the absolute path of the NEMU project.
• Set environment variable NOOP_HOME to the absolute path of the XiangShan project.
• Set environment variable AM_HOME to the absolute path of the AM project.
• Install mill. Refer to the Manual section in this guide.
• Clone this project and run make init to initialize submodules.

• Install Verilator, the open-source Verilog simulator.
• Run make emu to build the C++ simulator ./build/emu with Verilator.
• Refer to ./build/emu --help for run-time arguments of the simulator.
• Refer to Makefile and verilator.mk for more information.

Example:

make emu CONFIG=MinimalConfig EMU_THREADS=2 -j10
./build/emu -b 0 -e 0 -i ./ready-to-run/coremark-2-iteration.bin --diff ./ready-to-run/riscv64-nemu-interpreter-so

Troubleshooting Guide

The implementation of XiangShan is inspired by several key papers. We list these papers in XiangShan document, see: Acknowledgements. We very much encourage and expect that more academic innovations can be realised based on XiangShan in the future.

Copyright © 2020-2025 Institute of Computing Technology, Chinese Academy of Sciences.

Copyright © 2021-2025 Beijing Institute of Open Source Chip

Copyright © 2020-2022 by Peng Cheng Laboratory.

XiangShan is licensed under Mulan PSL v2.