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1. Standard_Cell_Project Standard_Cell_Project Public

   Design of a 7-track standard cell

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2. Layout-Design Layout-Design Public

   The main objective was doing this project is to get familiar with Layout designing steps and Physical Verification Checks such as DRC, LVS and Parasitic Extraction. This Project was done using APDK…

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3. 32bit-ALU 32bit-ALU Public

   Forked from enquestor/32bit-ALU

   Verilog 32-bit ALU.

   Verilog