OpenTitan: Open source silicon root of trust

Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

RSD: RISC-V Out-of-Order Superscalar Processor

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

A directory of Western Digital’s RISC-V SweRV Cores

A Linux-capable RISC-V multicore for and by the world

The root repo for lowRISC project and FPGA demos.

This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain accelerated by a PULP cluster with 8 cores.

RISC-V CPU Core

⛔ DEPRECATED ⛔ Lean but mean RISC-V system!

PsPIN: A RISC-V in-network accelerator for flexible high-performance low-power packet processing