opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

RTL, Cmodel, and testbench for NVDLA

IC design and development should be faster，simpler and more reliable

SERV - The SErial RISC-V CPU

OpenXuantie - OpenC910 Core

32-bit Superscalar RISC-V CPU

RISC-V XV6/Linux SoC, marchID: 0x2b

A tiny Open POWER ISA softcore written in VHDL 2008

mor1kx - an OpenRISC 1000 processor IP core

NESTang is an FPGA Nintendo Entertainment System implemented with Sipeed Tang Primer 25K, Nano 20K and Primer 20K boards

OpenXuantie - OpenC906 Core

ao486 port for MiSTer

Revengineered ancient PDP-11 CPUs, originals and clones

OpenXuantie - OpenE902 Core

OpenXuantie - OpenE906 Core

Pano Logic G2 Reverse Engineering Project

MIPSfpga+ allows loading programs via UART and has a switchable clock

Light-weight RISC-V RV32IMC microcontroller core.

OpenSPARC-based SoC

IBM PC Compatible SoC for a commercially available FPGA board

VexRiscv-SMP integration test with LiteX.

An example OMI Device FPGA with 2 DDR4 memory ports

RISCV Implementation in Verilog on Intel Quartus