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Starred repositories

3 results for source starred repositories written in Verilog
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SERV - The SErial RISC-V CPU

Verilog 1,668 231 Updated Oct 17, 2025

Rigel is a language for describing image processing hardware embedded in Lua. Rigel can compile to Verilog hardware designs for Xilinx FPGAs, and also can compile to fast x86 test code using Terra.

Verilog 56 9 Updated Sep 15, 2020

This repo is for Edge Vision SoC framework, which facilitates quick porting of users' design for Edge AI and Vision solutions.

Verilog 24 12 Updated Jun 4, 2025