Digital Design with Chisel

Project template for wafer.space MPW runs using the gf180mcu PDK

A configurable SRAM generator

Submission template for Tiny Tapeout IHP shuttles - Chisel HDL Projects

LibreLane full-chip flow template for IHP SG13G2 OpenPDK

The SoC for the introduction to chip design course spring 2026

Self-contained RTL to GDS flow for simple chip designs

A library of approximate arithmetic units in Chisel.

Subsystem DTU test tapeout

Using DFFRAM in a Tiny Tapeout design

LISA (Little ISA) 8-Bit Microcontroller SOC

Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.

A teaching-focused RISC-V CPU design used at UC Davis

Agile Hardware Design Course

ASIC implementation flow infrastructure, successor to OpenLane

3-stage RV32IMACZb* processor with debug

An open-source implementation of the VADL processor description language.

Naive Educational RISC V processor

An implementation of RISC-V

KLayout Main Sources

Tiny, fast(ish), self-contained, fully loaded printf, sprinf etc. implementation; particularly useful in embedded systems.

CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional cache…

A Risc-V SoC for Tiny Tapeout

RISC-V RV32E core designed for minimal area