SMAUG: Simulating Machine Learning Applications Using Gem5-Aladdin

GPGPU-Sim provides a detailed simulation model of contemporary NVIDIA GPUs running CUDA and/or OpenCL workloads. It includes support for features such as TensorCores and CUDA Dynamic Parallelism as…

NPUsim: Full-Model, Cycle-Level, and Value-Aware Simulator for DNN Accelerators

Materials, slides, and workspace for the gem5 bootcamp 2024

RISC-V IOMMU Specification

The official repository for the gem5 computer-system architecture simulator.

RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores

Learning gem5 is a work-in-progress book to help gem5 users get started using gem5.

The Herd toolsuite to deal with .cat memory models (version 7.xx)

SST Structural Simulation Toolkit Parallel Discrete Event Core and Services

Cycle-accurate C++ & SystemC simulator for the RISC-V GPGPU Ventus

GPGPU processor supporting RISCV-V extension, developed with Chisel HDL

GPGPU supporting RISCV-V, developed with verilog HDL

RTL data structure

体系结构研讨 + ysyx高阶大纲 (WIP

ESESC: A Fast Multicore Simulator

An open-source microcontroller system based on RISC-V

ChampSim is an open-source trace based simulator maintained at Texas A&M University and through the support of the computer architecture community.

Open-source non-blocking L2 cache

Jiezi simulator from Penglai

A Virtual platform using DBT-RISE-RISCV capable of running unmodified FreeRTOS

New release of the systemc libraries

A Primer on Memory Consistency and Cache Coherence (Second Edition) 翻译计划

A fast and scalable x86-64 multicore simulator