Multi-height resynthesis and legalization

An analytical VLSI placer

OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

Resynthesis library for post-mapping optimization

An advanced header-only exact synthesis library

Binary releases for HeteroSTA

EPFL logic synthesis benchmarks

E-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for Logic Synthesis (DAC 2024)

Research paper based on or related to ABC.

A Logic Synthesis tool based on "Mockturtle: EPFL Logic Synthesis Library " and "ABC: System for Sequential Logic Synthesis and Formal Verification""

GPU-based logic synthesis tool

C++ logic network library

ABC: System for Sequential Logic Synthesis and Formal Verification

First Open-Source Industry-Specific Model for Semiconductors

Official implementation of paper "Open3DBench: Open-Source Benchmark for 3D-IC Backend Implementation and PPA Evaluation".

CircuitNet: An Open-Source Dataset for Machine Learning Applications in Electronic Design Automation (EDA)

Deep learning toolkit-enabled VLSI placement

Initial version of CircuitGCL

[NeurIPS 2020] Balanced Meta-Softmax for Long-Tailed Visual Recognition

Few-shot Learning on AMS Circuits and Its Application to Parasitic Capacitance Prediction

simple_version of CirGPS

BUPTGraduateThesis提供北京邮电大学研究生学位论文LaTeX文档类，其符合北邮研究生院2014年11月发布的《关于研究生学位论文格式的统一要求》，目前已根据2017年标准修正格式、添加英文扉页，已根据2023年标准修正格式、添加答辩小组名单页，已根据2024年标准修正格式