PicoRV32 - A Size-Optimized RISC-V CPU

Verilog PCI express components

32-bit Superscalar RISC-V CPU

An FPGA-based Field Oriented Control (FOC) for driving BLDC/PMSM motor. 基于FPGA的FOC控制器，用于驱动BLDC/PMSM电机。

synthesiseable ieee 754 floating point library in verilog

SPI Slave for FPGA in Verilog and VHDL

Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

SOFA (Skywater Opensource FPGAs) based on Skywater 130nm PDK and OpenFPGA

Fixed Point Math Library for Verilog

Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.

IDEA project source files

Gateware / Firmware / BuildRoot to run linux on iCE40 / iCEBreaker

Mathematical Functions in Verilog

WIP 100BASE-TX PHY

A pipelined RISC-V processor

Robotic Application Processor

CPOL=0, CPHA=0 SPI core for practicing formal verification with yosys

The source code for the XTRX FPGA image

Kogge-Stone Adder in Verilog

Top level for the November shuttle

A lightweight version of the efabless Ravenna RISC-V processor chip design files for public access

PicoRV32 - A Size-Optimized RISC-V CPU

FPGA HDL for conan fpga board with klipper