Stars
FireSim: Fast and Effortless FPGA-accelerated Hardware Simulation with On-Prem and Cloud Flexibility
Benchmarks for Accelerator Design and Customized Architectures
Public Release Repo for PhIDO, currently maintained.
ASIC implementation flow infrastructure, successor to OpenLane
A configurable and approachable tool for FPGA debugging and rapid prototyping.
Open-source ECP5 toolchain, including synthesis, place-and-route, and Risc-V GCC
A machine learning accelerator core designed for energy-efficient AI at the edge.
Full-throttle, wire-speed hardware implementation of Wireguard VPN, using low-cost Artix7 FPGA with opensource toolchain. If you seek security and privacy, nothing is private in our codebase. Our d…
Domain-specific language designed to streamline the development of high-performance GPU/CPU/Accelerators kernels
WISHBONE SD Card Controller IP Core
Trying to figure various CPU things out
Resona is a RISC-V DSP simulator with support for the RV32I base and 'P' (DSP) extension
RISC-V Superscalar Educational Simulator based on Tomasulo's Algorithm
HIP: C++ Heterogeneous-Compute Interface for Portability
Collection of all FPGA related PSI libraries in the correct folder strucutre. Each library is included as submodule.
A collection of common Bluespec interfaces/modules.
Rust DataBase Connectivity (RDBC) :: Common Rust API for database drivers
Tigon: A Distributed Database for a CXL Pod [OSDI '25]
Bringup-Bench is a collection of standalone minimal library and system dependence benchmarks useful for bringing up newly designed CPUs, accelerators, compilers and operating systems. You probably …
CPU inference for the DeepSeek family of large language models in C++