Contains the code examples from The UVM Primer Book sorted by chapters.

Reference examples and short projects using UVM Methodology

VIP for AXI Protocol

AMBA AHB 2.0 VIP in SystemVerilog UVM

UVM examples and projects

Maven Silicon project - AHB-to-APB Bridge Verification using UVM Methodology.

This asynchrounous FIFO deisgn and UVM verificaiton is one case study of me. The design is based on Cliff Cumming's paper and the UVM is coded by me(Xianghzi Meng)

UVM Testbench to verify serial transmission of data between SPI master and slave

UVM Generator

SystemVerilog UVM testbench example

UVM interactive debug library

Verification IP for AMBA APB Protocol

为了学习UVM验证相关知识，需要动手尝试实际的项目。作为一个初学者，难以接触到实际的项目，于是我从夏宇闻老师的《Verilog数字系统设计教程》一书中，挑选出一个简单的小设计，作为我的验证对象，并围绕它编写了UVM验证环境。

uvm auto generator

An UVM example of UART

General Purpose I/O agent written in UVM

Implements a simple UVM based testbench for a simple memory DUT.

This script builds the UVM register model, based on pre-defined address map in markdown (mk) style

UVM Test bench for a 8-bit ALU

AMBA AHB 5.0 VIP in SystemVerilog based on UVM

UVM VIP for Single Port RAM Synchronous Read/Write

UVM verification component and testbench generator tool

UVM and Systemverilog based test benches for functional verification of a RAM module

an infrastructure to implement arbitrary indirect registers on top of uvm