Verilog Ethernet components for FPGA implementation

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

Open source FPGA-based NIC and platform for in-network compute

RTL, Cmodel, and testbench for NVDLA

A small, light weight, RISC CPU soft core

Verilog PCI express components

Verilog library for ASIC and FPGA designers

An open source GPU based off of the AMD Southern Islands ISA.

The RIFFA development repository

A tiny Open POWER ISA softcore written in VHDL 2008

synthesiseable ieee 754 floating point library in verilog

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

NetFPGA 1G infrastructure and gateware

RIDECORE (RIsc-v Dynamic Execution CORE) is an Out-of-Order RISC-V processor written in Verilog HDL.

ao486 port for MiSTer

Defines a lossless compressed data format that is independent of CPU type, operating system, file system, and character set, and is suitable for compression using the XP10 algorithm.

Chisel implementation of the NVIDIA Deep Learning Accelerator (NVDLA), with self-driving accelerated

Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.

EDA physical synthesis optimization kit

Builds, flow and designs for the alpha release

FAST-9 Accelerator for Corner Detection

DPI module for UART-based console interaction with Verilator simulations