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Starred repositories

5 stars written in Verilog
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IC design and development should be faster,simpler and more reliable

Verilog 1,975 591 Updated Dec 31, 2021

OpenXuantie - OpenC910 Core

Verilog 1,358 361 Updated Jun 28, 2024

Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.

Verilog 369 98 Updated Feb 26, 2025

JKU IIC OSIC-Multitool for open-source IC (OSIC) design for SKY130.

Verilog 77 20 Updated Mar 28, 2025

"High density" digital standard cells for SKY130 provided by SkyWater.

Verilog 18 37 Updated Feb 22, 2023