Reed Solomon encoder written in verilog hardware description language

A 16-bit by 16-bit signed binary multiplier based on the Radix-4 Booth algorithm and Wallace Tree reduction

An FPGA-based Field Oriented Control (FOC) for driving BLDC/PMSM motor. 基于FPGA的FOC控制器，用于驱动BLDC/PMSM电机。

OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

KLayout Main Sources

Yosys Open SYnthesis Suite

LibreSilicon's Standard Cell Library Generator

OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/

This is chiplogo a logo generator for VLSI chips.

Open-source repository for a standard-cell library characterizer using complete open-source tools

Azadi (Freedom) is a 32-bit RISC-V CPU based System on Chip.

Awesome ASIC design verification

A simple CPU written by SpinaHDL

深度学习经典、新论文逐段精读

Open-source high-performance RISC-V processor

positioning using Time Delay of Arrival

小米游戏本黑苹果Clover配置

[Hackintosh] Configuration for Lenovo Thinkpad P50.